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Date 04/28/2025*
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Reviewed On MM/DD/YYYY*
Embedded systems development often uses many acronyms for buses, memory operations, communication protocols, and peripherals. Understanding these terms is critical for reading datasheets, designing firmware, and debugging systems.
Key Concepts & Takeaways
List of essential terms and acronyms:
| Acronym | Meaning | Quick Explanation |
|---|---|---|
| ADC | Analog to Digital Converter | Converts analog signals (e.g., sensor output) into digital values. |
| AHB | Advanced High-performance Bus | High-performance pipelined bus for fast memory/peripheral access. |
| AMBA | Advanced Microcontroller Bus Architecture | ARM standard for communication between CPU, memory, and peripherals. |
| APB | Advanced Peripheral Bus | Low-speed, low-power bus for simple peripherals (e.g., UART, Timer). |
| AXI | Advanced eXtensible Interface | A high-performance bus protocol used inside SoCs (e.g., ARM-based designs). |
| AXI4 | Advanced eXtensible Interface 4 | Latest AXI bus version; supports burst transactions and outstanding accesses. |
| AXI4-Lite | AXI4 Lite Protocol | Simplified version of AXI4 for simple register access. |
| CSR | Control and Status Register | Registers used to configure and monitor hardware modules. |
| DAC | Digital to Analog Converter | Converts digital values into analog output (e.g., for audio). |
| DMA | Direct Memory Access | Hardware module that moves data between memory and peripherals without CPU intervention. |
| DRAM | Dynamic Random-Access Memory | Volatile memory with higher density but slower access than SRAM. |
| ECC | Error Correction Code | Technique for detecting and correcting bit-level errors in memory or data. |
| FIFO | First In, First Out | Buffer type where first data written is first data read out. |
| FPGA | Field-Programmable Gate Array | Reconfigurable hardware used alongside CPUs in embedded systems. |
| GPIO | General-Purpose Input/Output | Simple programmable pins for reading or driving logical signals. |
| HLS | High-Level Synthesis | Converts C/C++ code into FPGA logic automatically. |
| I2C | Inter-Integrated Circuit | Two-wire serial bus (SDA, SCL) for low-speed communications between ICs. |
| ISR | Interrupt Service Routine | Special function executed when an interrupt occurs. |
| JTAG | Joint Test Action Group | Interface for debugging and programming hardware at low level. |
| MCU | Microcontroller Unit | Small computer on a single chip, often used in embedded systems. |
| MMU | Memory Management Unit | Hardware that handles virtual memory and address translation. |
| MPU | Memory Protection Unit | Simplified MMU; controls access permissions without full virtual memory. |
| NVM | Non-Volatile Memory | Memory that retains data without power (e.g., Flash, EEPROM). |
| PLL | Phase-Locked Loop | Circuit used to generate stable high-frequency clocks. |
| PPI | Private Peripheral Interrupts | Per-core interrupt sources used in multicore ARM processors. |
| PS/PL | Processing System / Programmable Logic | Terms used in Zynq SoCs: ARM cores (PS) + FPGA fabric (PL). |
| PWM | Pulse Width Modulation | Modulates duty cycle of a digital signal for control (e.g., motors, LEDs). |
| QSPI | Quad Serial Peripheral Interface | A high-bandwidth SPI protocol using 4 data lines, often used for flash memory. |
| RTOS | Real-Time Operating System | OS designed for deterministic task scheduling and handling deadlines. |
| SoC | System on Chip | Integrated circuit containing CPU, memory, and peripherals. |
| SPI | Serial Peripheral Interface | Synchronous serial communication with master/slave, using SCLK, MOSI, MISO, SS lines. |
| SRAM | Static Random-Access Memory | Fast, volatile memory typically used for caches. |
| TCM | Tightly Coupled Memory | Fast memory attached directly to the CPU, bypassing caches. |
| TMR | Triple Modular Redundancy | Fault-tolerant method duplicating critical circuits and using majority voting. |
| TrustZone | ARM Security Extension | Creates secure and non-secure hardware partitions for protected execution. |
| UART | Universal Asynchronous Receiver/Transmitter | Serial communication interface (TX/RX, no clock). |
Mnemonics / Memory Aids
- "SPI = Spin (clock), UART = Unclocked (no clock)"
- "DMA = Don't Move Anything (CPU), it’s automatic"
- "AXI = Highway of data inside the chip"
- "AXI for speed, APB for simple feeds." (AXI is high-speed, APB is low-speed)
- "TrustZone = Two Worlds, One Chip." (Secure & Non-Secure)
- "MMU = Virtualize; MPU = Protect."
Connections to Other Topics
- DMA, AXI, and FIFO are often combined in high-speed embedded designs (e.g., video processing).
- RTOS and ISR management is crucial for real-time behavior in mission-critical systems.
- UART, SPI, and I2C are everywhere in MCU peripheral communication.
- AXI4, APB, AHB, and AMBA are often found inside SoCs like Zynq, i.MX, STM32MP1.
- TrustZone, MMU, MPU are critical in IoT security, automotive, and medical devices.
- TCM is critical in real-time systems where cache misses are unacceptable.
- FPGA + HLS strategies are important in custom hardware acceleration (AI/ML edge).
Example Applications
- Using DMA to transfer ADC results to memory without CPU load.
- Setting up SPI to read from an external flash chip.
- Configuring GPIOs to control an LED or button input.
- Configuring TrustZone to separate secure bootloader and non-secure application code.
- Using AXI4-Lite to map a custom hardware peripheral into ARM memory space (PL side).
- Implementing ECC in a critical memory region for a satellite system.
Next Review Date
📅 05/15/2025